 Functional verification培訓 |
| 入學要求 |
|
學員學習本課程應具備下列基礎知識：
◆ 電路系統(tǒng)的基本概念。 |
|
班級規(guī)模及環(huán)境 |
|
為了保證培訓效果，增加互動環(huán)節(jié)，我們堅持小班授課，每期報名人數(shù)限3到5人，多余人員安排到下一期進行。 |
|
上課時間和地點 |
上課地點：【上海】：同濟大學(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】：電影大廈(地鐵一號線大劇院站)/深圳大學成教院 【北京分部】：北京中山/福鑫大樓 【南京分部】：金港大廈(和燕路) 【武漢分部】：佳源大廈（高新二路） 【成都分部】：領(lǐng)館區(qū)1號（中和大道） 【沈陽分部】：沈陽理工大學/六宅臻品 【鄭州分部】：鄭州大學/錦華大廈 【石家莊分部】：河北科技大學/瑞景大廈
近開課時間(周末班/連續(xù)班/晚班）：Functional verification培訓：2025年8月18日..用心服務..........--即將開課--........................ |
|
學時 |
◆課時： 共5天,30學時
◆外地學員：代理安排食宿（需提前預定）
☆注重質(zhì)量
☆邊講邊練
☆合格學員免費推薦工作
專注高端培訓17年，曙海提供的課程得到本行業(yè)的廣泛認可，學員的能力
得到大家的認同，受到用人單位的廣泛贊譽。
★實驗設備請點擊這兒查看★ |
|
新優(yōu)惠 |
|
◆團體報名優(yōu)惠措施：兩人95折優(yōu)惠，三人或三人以上9折優(yōu)惠 。注意：在讀學生憑學生證，即使一個人也優(yōu)惠500元。 |
|
質(zhì)量保障 |
|
1、培訓過程中，如有部分內(nèi)容理解不透或消化不好，可免費在以后培訓班中重聽；
2、培訓結(jié)束后,培訓老師留給學員手機和Email,免費提供半年的技術(shù)支持，充分保證培訓后出效果；
3、培訓合格學員可享受免費推薦就業(yè)機會。 。專注高端培訓13年，曙海提供的證書得到本行業(yè)的廣泛認可，學員的能力得到大家的認同，受到用人單位的廣泛贊譽。 |
Functional verification培訓
|
第一階段 Incisive Comprehensive Coverage
Course Description
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course explores Incisive? comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of SystemC, VHDL, Verilog?, and mixed-language designs. Not all coverage features are available with all languages.
The course discusses the collection and analysis of the following types of coverage:
- Code (block, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog covergroups
- Control-oriented functional coverage using PSL and SystemVerilog assertions
Learning Objectives
After completing this course you will be able to:
- Effectively use the Incisive comprehensive coverage with your SystemC, VHDL, Verilog, and mixed-language designs
第二階段 Incisive SystemC, VHDL, and Verilog Simulation
Course Description
This course addresses Incisive? mixed-language (SystemC?, VHDL, and Verilog?) event-driven digital simulation. The course takes you through the compilation, elaboration, simulation, and interactive debug process, at each step explaining the most commonly used options. This course treats the SystemC, VHDL, and Verilog languages equivalently. You can do the labs in your choice of language.
Learning Objectives
After completing this course you will be able to:
- Compile, elaborate, link, and simulate a design: Understand how to specify the inputs and outputs at each phase, configure the design, and control each process for effectiveness and optimal performance.
- Debug a design with the textual interactive simulation interface: Briefly examine most of the interactive commands for the purpose of understanding what capabilities are available and how you can use them in a script to drive batched regression tests; practice these capabilities in the context of a scripted debug scenario.
- Debug a design with the graphical interactive simulation interface: Examine many of the capabilities of the feature-rich SimVision graphical simulation analysis environment; practice these capabilities in the context of a scripted debug scenario.
- Utilize some of the other tools available to assist your simulation-related efforts to: Verify your platform's patch level, protect your intellectual property, “l(fā)int” your design and filter and sort the analysis report, manage your library of compiled design objects, compare simulation traces, package your design for transmittal, and much more.
- Optionally: Understand the issues involved with mixed-language instantiation, simulation, and debugging; examine the mechanics of interconnecting components of multiple languages; choose and simulate a mixed-language design configuration containing at least one HDL component and at least one SystemC component.
|
|
|
首頁 課程表 報名 在線聊 講師 品牌 QQ聊 活動 就業(yè)